1. Field of the Invention
This invention relates to a method of manufacturing a semiconductor device and to a semiconductor device. More particularly, the invention relates to a method of manufacturing a semiconductor device ideal when injecting an impurity into the lower portion of a device for forming wiring in a vertical transistor, and to a semiconductor device.
2. Description of Related Art
Advances in microfabrication of semiconductor devices in recent years have been accompanied by higher degrees of integration. A vertical transistor (e.g., see Patent Document 1) is known as one example of such a semiconductor device having a high degree of integration. In the case of a vertical transistor, layers of a drain region, channel region and source region are built up on a silicon substrate in the vertical direction, i.e., in a direction perpendicular to the main surface of the silicon substrate. For this reason, the area of the silicon substrate occupied in a vertical transistor can be reduced in comparison with a transistor having a planar structure.
An example of a process for manufacturing buried wiring in a conventional vertical transistor will be described with reference to FIGS. 15 to 17. First, a mask pattern having circular openings arranged in a two-dimensional array as shown in FIG. 15A is formed on a silicon substrate 1 by photolithography. Next, the silicon substrate 1 is etched using the mask pattern as a mask, thereby forming silicon columns (referred to as “columnar patterns” below) 20. FIG. 15B is a sectional view of FIG. 15A taken along line a-a′.
Following the step shown in FIGS. 15A, 15B, a side wall (insulating film) 21 is formed on the side surface of the columnar pattern 20 and an impurity is injected to thereby form an impurity-injection layer 22, as illustrated in FIGS. 16A, 16B. Next, as shown in FIGS. 17A, 17B, a separate sidewall 23 is further formed on the outer side of the side wall 21, after which etching is carried out and the patterning of buried wiring 24. It should be noted that when the etching is performed, the impurity-injection layer 22 that has been formed on the top surface of the columnar pattern 20 is removed.    [Patent Document 1]    Japanese Patent Kokai Publication No. JP2005-19741A